1. Field of the Invention
The invention relates to a crack stopping structure, and more particularly, to a crack stopping structure disposed on the scribe line of a wafer.
2. Description of the Prior Art
The manufacturing flow of the integrated circuit can be mainly distinguish into three stages as follows: (1) the manufacturing of the wafer, (2) the fabrication of the integrated circuit, and (3) the cutting, electric testing, sorting, and packaging of the integrated circuit. When fabricating the integrated circuit on the wafer, the whole wafer is divided uniformly into many overlapping dies, and the adjacent dies are separated by a scribe line. The cutting step of the integrated circuit utilizes a cutter to cut the wafer into individual dies along the scribe lines.
In recent years, the high integration semiconductor process, with an inter-metal dielectric layer collocated by the dual damascene technology and the use of low dielectric materials, is the most popular metal interconnect technology to date. Due to the low resistance of copper, and the low dielectric material, the RC delay between the metal wires is greatly reduced. However, for achieving low dielectric property, many of low dielectric materials have loose, and weak mechanical strength structures, and are fragile. Therefore a chip crack often occurs from lateral cutting stress while performing wafer dicing. The chip crack damages the die seal ring region of the wafer that protects the die region and induces metal layer delamination. This causes high infant mortality in products, thereby reducing yield in subsequent electric test processes.